gic.h

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#pragma once
 
#include <etl/io_port.h>
 
#include <cstddef>
#include <cstdint>
 
class Gic {
 public:
  static constexpr const char* kCompatibleName = "arm,gic-v3";
 
  static constexpr size_t kSgiBase = 0;
  static constexpr size_t kSgiCount = 16;
  static constexpr size_t kPpiBase = 16;
  static constexpr size_t kPpiCount = 16;
  static constexpr size_t kSpiBase = 32;
  static constexpr size_t kSpiCount = 988;
 
  class Gicd {
   public:
    auto Enable(uint32_t intid) const -> void;
 
    auto EnableGrp1Ns() const -> void;
 
    auto Disable(uint32_t intid) const -> void;
 
    auto Clear(uint32_t intid) const -> void;
 
    [[nodiscard]] auto IsEnable(uint32_t intid) const -> bool;
 
    auto SetPrio(uint32_t intid, uint32_t prio) const -> void;
 
    auto SetConfig(uint32_t intid, uint32_t config) const -> void;
 
    auto SetTarget(uint32_t intid, uint32_t cpuid) const -> void;
 
    auto SetupSpi(uint32_t intid, uint32_t cpuid) const -> void;
 
 
    explicit Gicd(uint64_t _base_addr);
    Gicd() = default;
    Gicd(const Gicd&) = delete;
    Gicd(Gicd&&) = delete;
    auto operator=(const Gicd&) -> Gicd& = delete;
    auto operator=(Gicd&&) -> Gicd& = default;
    ~Gicd() = default;
 
   private:
    static constexpr uint32_t kCtlr = 0x0000;
    static constexpr uint32_t kCtlrEnableGrp1Ns = 0x2;
 
    struct GicdCtlr {
      uint32_t rwp : 1;
      uint32_t reserved1 : 23;
      uint32_t e1nwf : 1;
      uint32_t ds : 1;
      uint32_t are_ns : 1;
      uint32_t are_s : 1;
      uint32_t reserved0 : 1;
      uint32_t enable_grp1_s : 1;
      uint32_t enable_grp1_ns : 1;
      uint32_t enable_grp0 : 1;
    };
 
    static constexpr uint32_t kTyper = 0x0004;
    static constexpr uint32_t kTyperItLinesNumberMask = 0x1F;
 
    struct GicdTyper {
      uint32_t reserved1 : 6;
      uint32_t no1n : 1;
      uint32_t a3v : 1;
      uint32_t idbits : 5;
      uint32_t dvis : 1;
      uint32_t lpis : 1;
      uint32_t mbis : 1;
      uint32_t num_lpis : 5;
      uint32_t security_extn : 1;
      uint32_t reserved0 : 2;
      uint32_t cpu_number : 3;
      uint32_t it_lines_number : 5;
    };
 
    static constexpr uint32_t kIidr = 0x0008;
 
    struct GicdIidr {
      uint32_t product_id : 8;
      uint32_t reserved0 : 4;
      uint32_t variant : 4;
      uint32_t revision : 4;
      uint32_t implementer : 12;
    };
 
    static constexpr uint32_t kFctlr = 0x0020;
    static constexpr uint32_t kSac = 0x0024;
    static constexpr uint32_t kSetSpiNsr = 0x0040;
    static constexpr uint32_t kClrSpiNsr = 0x0048;
    static constexpr uint32_t kSetSpiSr = 0x0050;
    static constexpr uint32_t kClrSpiSr = 0x0058;
 
    static constexpr uint32_t kIgrouprn = 0x0080;
 
    [[nodiscard]] __always_inline auto Igrouprn(uint64_t n) const -> uint64_t {
      return kIgrouprn + n * 4;
    }
 
    static constexpr uint32_t kIsEnablern = 0x0100;
    static constexpr uint32_t kIsEnablernSize = 32;
 
    [[nodiscard]] __always_inline auto Isenablern(uint64_t n) const
        -> uint64_t {
      return kIsEnablern + n * 4;
    }
 
    static constexpr uint32_t kIcEnablern = 0x0180;
    static constexpr uint32_t kIcEnablernSize = 32;
 
    [[nodiscard]] __always_inline auto Icenablern(uint64_t n) const
        -> uint64_t {
      return kIcEnablern + n * 4;
    }
 
    static constexpr uint32_t kIsPendrn = 0x0200;
 
    static constexpr uint32_t kIcPendrn = 0x0280;
    static constexpr uint32_t kIcPendrnSize = 32;
 
    [[nodiscard]] __always_inline auto Icpendrn(uint64_t n) const -> uint64_t {
      return kIcPendrn + n * 4;
    }
 
    static constexpr uint32_t kIsActivern = 0x0300;
    static constexpr uint32_t kIcActivern = 0x0380;
 
    static constexpr uint32_t kIpriorityrn = 0x0400;
    static constexpr uint32_t kIpriorityrnSize = 4;
    static constexpr uint32_t kIpriorityrnBits = 8;
    static constexpr uint32_t kIpriorityrnBitsMask = 0xFF;
 
    [[nodiscard]] __always_inline auto Ipriorityrn(uint64_t n) const
        -> uint64_t {
      return kIpriorityrn + n * 4;
    }
 
    static constexpr uint32_t kItargetsrn = 0x0800;
    static constexpr uint32_t kItargetsrnSize = 4;
    static constexpr uint32_t kItargetsrnBits = 8;
    static constexpr uint32_t kItargetsrnBitsMask = 0xFF;
 
    [[nodiscard]] __always_inline auto Itargetsrn(uint64_t n) const
        -> uint64_t {
      return kItargetsrn + n * 4;
    }
 
    static constexpr uint32_t kIcfgrn = 0x0C00;
    static constexpr uint32_t kIcfgrnSize = 16;
    static constexpr uint32_t kIcfgrnBits = 2;
    static constexpr uint32_t kIcfgrnBitsMask = 0x3;
    static constexpr uint32_t kIcfgrnLevelSensitive = 0;
    static constexpr uint32_t kIcfgrnEdgeTriggered = 1;
 
    [[nodiscard]] __always_inline auto Icfgrn(uint64_t n) const -> uint64_t {
      return kIcfgrn + n * 4;
    }
 
    static constexpr uint32_t kIgrpmodrn = 0x0D00;
    static constexpr uint32_t kNsacrn = 0x0E00;
    static constexpr uint32_t kIroutern = 0x6000;
    static constexpr uint32_t kChipsr = 0xC000;
    static constexpr uint32_t kDchipr = 0xC004;
    static constexpr uint32_t kChiprn = 0xC008;
    static constexpr uint32_t kIclarn = 0xE000;
    static constexpr uint32_t kIcerrrn = 0xE100;
    static constexpr uint64_t kCfgid = 0xF000;
    static constexpr uint32_t kPidr4 = 0xFFD0;
    static constexpr uint32_t kPidr5 = 0xFFD4;
    static constexpr uint32_t kPidr6 = 0xFFD8;
    static constexpr uint32_t kPidr7 = 0xFFDC;
    static constexpr uint32_t kPidr0 = 0xFFE0;
    static constexpr uint32_t kPidr1 = 0xFFE4;
    static constexpr uint32_t kPidr2 = 0xFFE8;
    static constexpr uint32_t kPidr3 = 0xFFEC;
    static constexpr uint32_t kCidr0 = 0xFFF0;
    static constexpr uint32_t kCidr1 = 0xFFF4;
    static constexpr uint32_t kCidr2 = 0xFFF8;
    static constexpr uint32_t kCidr3 = 0xFFFC;
 
    uint64_t base_addr_{0};
 
    [[nodiscard]] __always_inline auto Read(uint32_t off) const -> uint32_t {
      etl::io_port_ro<uint32_t> reg{reinterpret_cast<void*>(base_addr_ + off)};
      return reg.read();
    }
 
    __always_inline auto Write(uint32_t off, uint32_t val) const -> void {
      etl::io_port_wo<uint32_t> reg{reinterpret_cast<void*>(base_addr_ + off)};
      reg.write(val);
    }
  };
 
  class Gicr {
   public:
    auto Enable(uint32_t intid, uint32_t cpuid) const -> void;
 
    auto Disable(uint32_t intid, uint32_t cpuid) const -> void;
 
    auto Clear(uint32_t intid, uint32_t cpuid) const -> void;
 
    auto SetPrio(uint32_t intid, uint32_t cpuid, uint32_t prio) const -> void;
 
    auto SetUp() const -> void;
 
    auto SetupPpi(uint32_t intid, uint32_t cpuid) const -> void;
 
    auto SetupSgi(uint32_t intid, uint32_t cpuid) const -> void;
 
 
    explicit Gicr(uint64_t _base_addr);
    Gicr() = default;
    Gicr(const Gicr&) = delete;
    Gicr(Gicr&&) = delete;
    auto operator=(const Gicr&) -> Gicr& = delete;
    auto operator=(Gicr&&) -> Gicr& = default;
    ~Gicr() = default;
 
   private:
    static constexpr uint32_t kStride = 0x20000;
 
    static constexpr uint32_t kCtlr = 0x0000;
    static constexpr uint32_t kIidr = 0x0004;
    static constexpr uint32_t kTyper = 0x0008;
 
    static constexpr uint32_t kWaker = 0x0014;
    static constexpr uint32_t kWakerProcessorSleepMask = 2;
    static constexpr uint32_t kWakerChildrenAsleepMask = 4;
 
    static constexpr uint32_t kFctlr = 0x0020;
    static constexpr uint32_t kPwrr = 0x0024;
    static constexpr uint32_t kClassr = 0x0028;
    static constexpr uint32_t kPropbaser = 0x0070;
    static constexpr uint32_t kPendbaser = 0x0078;
    static constexpr uint32_t kPidr4 = 0xFFD0;
    static constexpr uint32_t kPidr5 = 0xFFD4;
    static constexpr uint32_t kPidr6 = 0xFFD8;
    static constexpr uint32_t kPidr7 = 0xFFDC;
    static constexpr uint32_t kPidr0 = 0xFFE0;
    static constexpr uint32_t kPidr1 = 0xFFE4;
    static constexpr uint32_t kPidr2 = 0xFFE8;
    static constexpr uint32_t kPidr3 = 0xFFEC;
    static constexpr uint32_t kCidr0 = 0xFFF0;
    static constexpr uint32_t kCidr1 = 0xFFF4;
    static constexpr uint32_t kCidr2 = 0xFFF8;
    static constexpr uint32_t kCidr3 = 0xFFFC;
 
    static constexpr uint32_t kSgiBase = 0x10000;
 
    static constexpr uint32_t kIgroupr0 = kSgiBase + 0x0080;
    static constexpr uint32_t kIgroupr0Clear = 0;
    static constexpr uint32_t kIgroupr0Set = UINT32_MAX;
 
    static constexpr uint32_t kIsEnabler0 = kSgiBase + 0x0100;
    static constexpr uint32_t kIsEnabler0Size = 32;
 
    static constexpr uint32_t kIcEnabler0 = kSgiBase + 0x0180;
    static constexpr uint32_t kIcEnabler0Size = 32;
 
    static constexpr uint32_t kIsPendr0 = kSgiBase + 0x0200;
 
    static constexpr uint32_t kIcPendr0 = kSgiBase + 0x0280;
    static constexpr uint32_t kIcPendr0Size = 32;
 
    static constexpr uint32_t kIsActiver0 = kSgiBase + 0x0300;
    static constexpr uint32_t kIcActiver0 = kSgiBase + 0x0380;
    static constexpr uint32_t kIpriorityrn = kSgiBase + 0x0400;
    static constexpr uint32_t kIpriorityrnSize = 4;
    static constexpr uint32_t kIpriorityrnBits = 8;
    static constexpr uint32_t kIpriorityrnBitsMask = 0xFF;
 
    [[nodiscard]] __always_inline auto Ipriorityrn(uint64_t n) const
        -> uint64_t {
      return kIpriorityrn + n * 4;
    }
 
    static constexpr uint32_t kIcfgrn = 0x0C00;
 
    static constexpr uint32_t kIgrpmodr0 = 0x0D00;
    // kIgrpmodr0 kIgroupr0 Definition
    // 0b0        0b0       Secure Group 0 G0S
    // 0b0        0b1       Non-secure Group 1 G1NS
    // 0b1        0b0       Secure Group 1 G1S
    static constexpr uint32_t kIgrpmodr0Clear = 0;
    static constexpr uint32_t kIgrpmodr0Set = UINT32_MAX;
 
    static constexpr uint32_t kNsacr = 0x0E00;
    static constexpr uint32_t kMiscstatusr = 0xC000;
    static constexpr uint32_t kIerrvr = 0xC008;
    static constexpr uint32_t kSgidr = 0xC010;
    static constexpr uint32_t kCfgid0 = 0xF000;
    static constexpr uint32_t kCfgid1 = 0xF004;
 
    uint64_t base_addr_{0};
 
    [[nodiscard]] __always_inline auto Read(uint32_t cpuid, uint32_t off) const
        -> uint32_t {
      etl::io_port_ro<uint32_t> reg{
          reinterpret_cast<void*>(base_addr_ + cpuid * kStride + off)};
      return reg.read();
    }
 
    __always_inline auto Write(uint32_t cpuid, uint32_t off, uint32_t val) const
        -> void {
      etl::io_port_wo<uint32_t> reg{
          reinterpret_cast<void*>(base_addr_ + cpuid * kStride + off)};
      reg.write(val);
    }
  };
 
  auto SetUp() const -> void;
 
  auto Spi(uint32_t intid, uint32_t cpuid) const -> void;
 
  auto Ppi(uint32_t intid, uint32_t cpuid) const -> void;
 
  auto Sgi(uint32_t intid, uint32_t cpuid) const -> void;
 
 
  explicit Gic(uint64_t gicd_base_addr, uint64_t gicr_base_addr);
  Gic() = default;
  Gic(const Gic&) = delete;
  Gic(Gic&&) = delete;
  auto operator=(const Gic&) -> Gic& = delete;
  auto operator=(Gic&&) -> Gic& = default;
  ~Gic() = default;
 
 private:
  Gicd gicd_{};
  Gicr gicr_{};
};