SimpleKernel 1.17.0
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Public Attributes | List of all members
Gic::Gicd::GicdTyper Struct Reference

GICD_TYPER, Interrupt Controller Type Register. More...

Collaboration diagram for Gic::Gicd::GicdTyper:
Collaboration graph

Public Attributes

uint32_t reserved1: 6
 [31:26] Reserved, returns 0b000000
 
uint32_t no1n: 1
 [25] No1N 1 of N SPI
 
uint32_t a3v: 1
 [24] A3V Affinity level 3 values
 
uint32_t idbits: 5
 [23:19] IDbits Interrupt identifier bits
 
uint32_t dvis: 1
 [18] DVIS Direct virtual LPI injection support
 
uint32_t lpis: 1
 [17] LPIS Indicates whether the implementation supports LPIs
 
uint32_t mbis: 1
 [16] MBIS Message-based interrupt support
 
uint32_t num_lpis: 5
 
uint32_t security_extn: 1
 [10] SecurityExtn Security state support
 
uint32_t reserved0: 2
 [9:8] Reserved, returns 0b00000
 
uint32_t cpu_number: 3
 
uint32_t it_lines_number: 5
 

Detailed Description

GICD_TYPER, Interrupt Controller Type Register.

See also
https://developer.arm.com/documentation/101206/0003/Programmers-model/Distributor-registers–GICD-GICDA–summary/GICD-TYPER–Interrupt-Controller-Type-Register?lang=en

Definition at line 153 of file gic.h.

Member Data Documentation

◆ a3v

uint32_t Gic::Gicd::GicdTyper::a3v

[24] A3V Affinity level 3 values

Definition at line 159 of file gic.h.

◆ cpu_number

uint32_t Gic::Gicd::GicdTyper::cpu_number

[7:5] CPUNumber Returns 0b000 because GICD_CTLR.ARE==1 (ARE_NS & ARE_S)

Definition at line 177 of file gic.h.

◆ dvis

uint32_t Gic::Gicd::GicdTyper::dvis

[18] DVIS Direct virtual LPI injection support

Definition at line 163 of file gic.h.

◆ idbits

uint32_t Gic::Gicd::GicdTyper::idbits

[23:19] IDbits Interrupt identifier bits

Definition at line 161 of file gic.h.

◆ it_lines_number

uint32_t Gic::Gicd::GicdTyper::it_lines_number

[4:0] ITLinesNumber Returns the maximum SPI INTID that this GIC-600AE implementation supports, given by 32×(ITLinesNumber + 1) − 1

Definition at line 181 of file gic.h.

◆ lpis

uint32_t Gic::Gicd::GicdTyper::lpis

[17] LPIS Indicates whether the implementation supports LPIs

Definition at line 165 of file gic.h.

◆ mbis

uint32_t Gic::Gicd::GicdTyper::mbis

[16] MBIS Message-based interrupt support

Definition at line 167 of file gic.h.

◆ no1n

uint32_t Gic::Gicd::GicdTyper::no1n

[25] No1N 1 of N SPI

Definition at line 157 of file gic.h.

◆ num_lpis

uint32_t Gic::Gicd::GicdTyper::num_lpis

[15:11] num_LPIs Returns 0b00000 because GICD_TYPER.IDbits indicates the number of LPIs that the GIC supports

Definition at line 170 of file gic.h.

◆ reserved0

uint32_t Gic::Gicd::GicdTyper::reserved0

[9:8] Reserved, returns 0b00000

Definition at line 174 of file gic.h.

◆ reserved1

uint32_t Gic::Gicd::GicdTyper::reserved1

[31:26] Reserved, returns 0b000000

Definition at line 155 of file gic.h.

◆ security_extn

uint32_t Gic::Gicd::GicdTyper::security_extn

[10] SecurityExtn Security state support

Definition at line 172 of file gic.h.

The documentation for this struct was generated from the following file: